At present, CMOS integrated circuits (IC) are used widely to form a semiconductor IC unit such as a microprocessor, etc. A CMOS IC consumes an electric power in two ways; dynamic power consumption and static power consumption. The dynamic power consumption is caused by charging and discharging at a switching time and the static power consumption is caused by a subthreshold leakage current. The dynamic power consumption consumes a large current in proportion to the square of a supply voltage VDD, so the supply voltage should be lowered to save the power consumption of the object CMOS IC effectively. In recent years, the supply voltage is thus getting lower and lower to cope with such an object.
On the other hand, some of the power-saving microprocessors available at present are provided with a power management feature and its processor is provided with a plurality of operation modes, so that supply of the clock to an active unit is stopped at its standby time according to the set operation mode.
Since the supply of the clock is stopped such way, it is possible to reduce unnecessary dynamic power consumption in such an active unit as much as possible. However, the static power consumption caused by a subthreshold leakage current cannot be reduced and still remains on the same level at this time.
The operation speed of a CMOS circuit drops at a low supply voltage. In order to prevent such a speed reduction of a CMOS circuit, therefore, the threshold voltage of the MOS transistor must be lowered in conjunction with the drop of the supply voltage. If a threshold voltage is lowered, however, the subthreshold leakage current increases extremely. And, as the supply voltage is getting lower, the static power consumption increases more remarkably due to the subthreshold leakage current, which has not been so much conventionally. This is why it is now urgently required to realize a semiconductor IC unit such as a microprocessor, which can satisfy both fast operation and low power consumption properties.
In order to solve the above problem, for example, the official gazette of Unexamined Published Japanese Patent Application No. Hei-6-54396 has proposed a method for controlling a threshold voltage of MOS transistors by setting a variable substrate bias.
The substrate bias is set to the power source potential for PMOS (P-channel MOS transistors) and the ground potential for NMOS (N-channel MOS transistors) in the active state when the object CMOS circuit is required for a fast operation. On the other hand, in the standby state in which the CMOS is not required for any fast operation, the substrate bias is set to a potential higher than the supply voltage for PMOS and lower than the supply voltage for NMOS (hereafter, this operation will often be referred to as “applying a bias voltage to a substrate”).
With such a setting of a substrate bias voltage in the standby state, it becomes possible to raise the threshold level of the MOS transistors composing the object CMOS circuit, thereby reducing the static power consumption caused by a subthreshold leakage current.